Load GDTR ( Global Descriptor Table Register) from memory. Some but not all of the instructions are available in real mode as well. The new instructions added in 80286 add support for x86 protected mode. Takes two operands: the amount of storage to be allocated on the stack and the nesting level of the procedure. Modifies stack for entry to procedure for high level language.
#Pin stack at las collins software
Raises software interrupt 5 if test fails 0x83/6 (since 80186)Īdded in specific processors Added with 80186/ 80188 Instruction R : = : r / m A spinlock typically uses xchg as an atomic operation. Waits until BUSY# pin is inactive (used with floating-point unit) If ( DF = 0 ) * ES : DI ++ = AX else * ES : DI - = AX Ġx28. May be used with a REP prefix to repeat the instruction CX times. If ( DF = 0 ) * ES : DI ++ = AL else * ES : DI - = AL May be used with a REP prefix to repeat the instruction CX times.ĠxC0. May be used with a REP prefix to repeat the instruction CX times.Ĭompare word string. 0xD3/7Īlternative 1-byte encoding of SBB AL, AL is available via undocumented SALC instructionĠx18. Shift Arithmetically left (signed shift left)ĠxC0. The assembler will translate these to a RETN or a RETF depending on the memory model of the target system.ĠxC0. (1) port = AL (2) port = AL (3) port = AX (4) port = AX ( LOOPE, LOOPNE, LOOPNZ, LOOPZ) if ( x & - CX ) goto lbl Ĭopies data from one location to another, (1) r/m = r (2) r = r/m If ( DF = 0 ) AX = * SI ++ else AX = * SI. If ( DF = 0 ) AL = * SI ++ else AL = * SI. ( JA, JAE, JB, JBE, JC, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ)Ġx70.
(1) AL = port (2) AL = port (3) AX = port (4) AX = port May be used with a REP prefix to repeat the instruction CX times.Ĭompare words. 0x83/7 (since 80186)Ĭompare bytes in memory. Push eip eip points to the instruction directly after the callĠx38. Only base 10 version (Operand is 0xA) is documented, see notes for AADĭestination = destination + source + carry_flagĠx10. NEC V20 and V30 (and possibly other NEC V-series CPUs) always use base 10, and ignore the argument, causing a number of incompatibilities Later Intel's documentation has the generic form too. Original 8086/8088 instructions Original 8086/8088 instruction setĨ086/8088 datasheet documents only base 10 version of the AAD instruction ( opcode 0xD5 0x0A), but any other base will work.
The updated instruction set is also grouped according to architecture ( i386, i486, i686) and more generally is referred to as (32-bit) x86 and (64-bit) x86-64 (also known as AMD64). Most if not all of these instructions are available in 32-bit mode they just operate on 32-bit registers ( eax, ebx, etc.) and values instead of their 16-bit ( ax, bx, etc.) counterparts.
#Pin stack at las collins full
Below is the full 8086/8088 instruction set of Intel (81 instructions total).
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